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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev.? a 06/28/2011 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is62c25616bl, IS65C25616BL features ? high-speed access time: 45 ns ? low active power: 50 mw (typical) ? low standby power: 10 mw (typical) cmos standby ? ttl compatible interface levels ? single 5v 10% power supply ? fully static operation: no clock or refresh required ? package: 44-pin tsop (type ii) ? commercial, industrial and automotive temper- ature ranges available ? lead-free available description the issi is62c25616bl and IS65C25616BL are high- speed, 4,194,304-bit static rams organized as 262,144 words by 16 bits. they are fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte (lb) access. the is62c25616bl and IS65C25616BL are packaged in the jedec standard 44-pin tsop (type ii). functional block diagram july ?2011 a0-a17 ce oe we 256k x 16 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb 256k?x?16?high-speed?cmos? static?ram
2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ?????????????? rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? pin configurations* pin?descriptions a0-a17 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 ce i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 a17 44-pin? tsop? (type?ii) *please contact issi at sram@issi.com for availability of 48-pin bga and 44-pin soj packages.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? truth ? table ? ? ? ? ? ? ? i/o?pin ? mode? we? ce? oe? lb ub ? i/o0-i/o7? i/o8-i/o15? v dd ?current? ? not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc 1 , i cc 2 x l x h h high-z high-z read h l l l h d out high-z i cc 1 , i cc 2 h l l h l high-z d out h l l l l d out d out write l l x l h d in high-z i cc 1 , i cc 2 l l x h l high-z d in l l x l l d in d in absolute?maximum? ratings (1) ? symbol? parameter ? value ? unit ? v term terminal voltage with respect to gnd C0.5 to +7.0 v t stg storage temperature C65 to +150 c p t power dissipation 1.5 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc?electrical? characteristics? (over operating range) ? symbol? parameter ? test ?conditions? ? min. ? max. ? unit ? v oh output high voltage v dd = min., i oh = C1.0 ma 2.4 v v ol output low voltage v dd = min., i ol = 2.1 ma 0.4 v v ih input high voltage (1) 2.2 v dd + 0.5 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd com. C1 1 a ind. C2 2 auto. C5 5 i lo output leakage gnd v out v dd com. C1 1 a outputs disabled ind. C2 2 auto. C5 5 note: 1. v ill ( min) = -2.0v ac (pulse width <10 ns). not 100% tested. v ihh ( max ) = v dd + 2.0v ac (pulse width <10 ns). not 100% tested. capacitance (1,2) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 5.0v.
4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ?????????????? rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? power ? supply? characteristics (1) ? (over operating range) ? ???????????????????????-45?ns ? ??????????????????????? ? symbol? parameter ? test ?conditions? ? min. ? max. ? ? unit i cc average operating ce = v il , com. 10 ma current v dd = max., ind. 10 i out = 0 ma, f = 0 auto. 10 i cc 1 v dd dynamic operating v dd = max., ce = v il com. 15 ma supply current i out = 0 ma, f = f max ind. 20 v in = v ih or v il auto. 25 typ. (2) 10 i sb 1 ttl standby current v dd = max., com. 1 ma (ttl inputs) v in = v ih or v il , ce v ih , ind. 1.5 f = 0 auto. 2 i sb 2 cmos standby v dd = max., com. 10 ma current (cmos inputs) ce v dd C 0.2v, ind. 15 v in v dd C 0.2v, auto. 35 or v in v ss + 0.2v, f = 0 typ. (2) 4 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. operating ?range ? range ? ambient? temperature ? v dd s peed?(ns) commercial 0c to +70c 5v 10% 45 industrial -40c to +85c 5v 10% 45 ? automotive -40c to +125c 5v 10% 45
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? read?cycle?switching? characteristics (1) ? (over operating range) ? -45? ? symbol? parameter ? min. ? max. ? ? unit t rc read cycle time 45 ns t aa address access time 45 ns t oha output hold time 3 ns t ace ce access time 45 ns t doe oe access time 20 ns t hzoe (2) oe to high-z output 0 15 ns t lzoe (2) oe to low-z output 5 ns t hzce (2) ce to high-z output 0 15 ns t lzce (2) ce to low-z output 5 ns t ba lb, ub access time 45 ns t hzb lb, ub to high-z output 0 15 ns t lzb lb, ub to low-z output 0 ns ac ? test?conditions ? parameter ? unit ? input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference level output load see figures 1 and 2 1838 30 pf including jig and scope 994 output 5v 1838 5 pf including jig and scope 994 output 5v notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested. figure 1 figure 2 ac ? test? loads
6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ?????????????? rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? read?cycle? no. ?2 (1,3)? (ce, oe and ub/lb controlled) ac ? waveforms read?cycle? no. ?1 (1,2) (address controlled) (ce = oe = v il , ub or lb = v il ) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce, ub, or lb = v il . 3. address is valid prior to or coincident with ce low transition. t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ub_cedr2.eps t hzb address oe ce lb, ub d out t hzce t ba t lzb data valid read1.eps previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? write?cycle?switching? characteristics (1,3) ? (over operating range) ? -45? ? symbol? parameter ? min. ? max. ? ? unit t wc write cycle time 45 ns t sce ce to write end 35 ns t aw address setup time 35 ns to write end t ha address hold from write end 0 ns t sa address setup time 0 ns t pwb lb, ub valid to end of write 35 ns t pwe 1 we pulse width (oe =high) 35 ns t pwe 2 we pulse width (oe =low) 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe (2) we low to high-z output 20 ns t lzwe (2) we high to low-z output 5 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ?????????????? rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (ce) [ (lb) = (ub) ] (we). ac ? waveforms write?cycle? no. ?1?(we? controlled) (1,2) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in data in valid t lzwe t sd ub_cewr1.eps
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? write?cycle? no. ?2 (oe is high during write cycle) (1,2) write?cycle? no. ?3 (oe is low during write cycle) (1) notes: 1. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd ub_cewr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd ub_cewr3.eps
10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ?????????????? rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? write?cycle? no. ?4 (ub/lb back to back write) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? data ?retention?switching? characteristics ? symbol? parameter ? test ?condition? ? min. ? ? max. ? unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 2.0v, ce v dd C 0.2v com. 10 ma v in v dd C 0.2v, or v in v ss + 0.2v ind. 15 auto. 35 typ. (1) 2 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note: ? 1. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. data ?retention? waveform ?(ce? controlled) vdd ce vdd - 0.2v t sdr t rdr v dr ce gnd 4.5v data retention mode
12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ?????????????? rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? ordering? information: ?is62c25616bl industrial? range: ?C40c?to?+85c ? speed?(ns)? order ? part?no. ? package 45 is62c25616bl-45ti 44-pin tsop-ii is62c25616bl-45tli 44-pin tsop-ii, lead-free automotive ? range: ?C40c?to?+125c ? speed?(ns)? order ? part?no. ? package 45 IS65C25616BL-45tla3 44-pin tsop-ii, lead-free
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev.? a 06/28/2011 is62c25616bl, IS65C25616BL ? 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline

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